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CS5361 114 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
24-bit Conversion 114 dB Dynamic Range -105 dB THD+N System Sampling Rates up to 192 kHz 135 mW Power Consumption High-pass Filter and DC Offset Calibration Differential Analog Architecture Overflow Detection Pin-compatible with the CS5381
General Description
digital audio systems. It performs sampling, analog-todigital conversion, and anti-alias filtering. The CS5361 generates 24-bit values for both left and right inputs in serial form at sample rates up to 192 kHz per channel.
Advanced Multi-bit Delta-sigma Architecture The CS5361 is a complete analog-to-digital converter for
The CS5361 uses a 5th-order, multi-bit, delta-sigma modulator followed by digital filtering and decimation. This removes the need for an external anti-alias filter. The ADC uses a differential architecture which provides excellent noise rejection. The CS5361 is ideal for audio systems requiring wide dyapplications include A/V receivers, DVD-R, CD-R, digital mixing consoles, and effects processors. ORDERING INFORMATION CS5361-KSZ -10 to 70C 24-pin SOIC Lead Free CS5361-KZZ -10 to 70C 24-pin TSSOP Lead Free CS5361-DZZ -40 to 85C 24-pin TSSOP Lead Free CDB5361 Evaluation Board
Supports Logic Levels Between 5 and 2.5 V namic range, negligible distortion, and low noise. These
VQ
REFGND
OVFL
VL SCLK
LRCK SDOUT
MCLK
FILT+
Voltage Reference
Serial Output Interface
RST I2S/LJ M/S HPF MDIV
AINLAINL+ S/H
+ -
LP Filter
Digital Decimation Filter
High Pass Filter
DAC AINRAINR+ S/H DAC + LP Filter Digital Decimation Filter High Pass Filter MODE0 MODE1
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Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
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CS5361
TABLE OF CONTENTS
1.0 CHARACTERISTICS AND SPECIFICATIONS ...................................................................... 4 Specified Operating Conditions ................................................................................................ 4 Absolute Maximum Ratings ...................................................................................................... 4 Analog Characteristics (CS5361-KSZ/KZZ).............................................................................. 5 Analog Characteristics (CS5361-DZZ) ..................................................................................... 6 Digital Filter Characteristics ...................................................................................................... 7 DC Electrical Characteristics .................................................................................................. 10 Digital Characteristics ............................................................................................................. 10 Switching Characteristics - Serial Audio Port.......................................................................... 11 2.0 PIN DESCRIPTIONS ............................................................................................................ 14 3.0 TYPICAL CONNECTION DIAGRAM .................................................................................... 15 4.0 APPLICATIONS .................................................................................................................... 16 4.1 Operational Mode/Sample Rate Range Select ................................................................ 16 4.2 System Clocking .............................................................................................................. 16 4.2.1 Slave Mode ......................................................................................................... 16 4.2.2 Master Mode ....................................................................................................... 17 4.3 Power-up Sequence ........................................................................................................ 18 4.4 Analog Connections ......................................................................................................... 18 4.5 High-pass Filter and DC Offset Calibration ..................................................................... 19 4.6 Overflow Detection ........................................................................................................... 19 4.6.1 OVFL Output Timing ........................................................................................... 19 4.7 Grounding and Power Supply Decoupling ....................................................................... 19 4.8 Synchronization of Multiple Devices ................................................................................ 19 5.0 PARAMETER DEFINITIONS ................................................................................................ 20 6.0 PACKAGE DIMENSIONS .................................................................................................. 21 7.0 REVISION HISTORY ............................................................................................................ 23
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LIST OF FIGURES
Figure 1. Single Speed Mode Stopband Rejection ..................................................... 8 Figure 2. Single Speed Mode Transition Band ........................................................... 8 Figure 3. Single Speed Mode Transition Band (Detail) .............................................. 8 Figure 4. Single Speed Mode Passband Ripple ......................................................... 8 Figure 5. Double Speed Mode Stopband Rejection ................................................... 8 Figure 6. Double Speed Mode Transition Band ......................................................... 8 Figure 7. Double Speed Mode Transition Band (Detail) ............................................. 9 Figure 8. Double Speed Mode Passband Ripple ....................................................... 9 Figure 9. Quad Speed Mode Stopband Rejection ...................................................... 9 Figure 10. Quad Speed Mode Transition Band .......................................................... 9 Figure 11. Quad Speed Mode Transition Band (Detail) ............................................. 9 Figure 12. Quad Speed Mode Passband Ripple ........................................................ 9 Figure 13. Master Mode, Left Justified SAI .............................................................. 12 Figure 14. Slave Mode, Left Justified SAI ................................................................ 12 Figure 15. Master Mode, I2S SAI .............................................................................. 12 Figure 16. Slave Mode, I2S SAI ................................................................................ 12 Figure 17. OVFL Output Timing ............................................................................... 12 Figure 18. Left Justified Serial Audio Interface ......................................................... 13 Figure 19. I2S Serial Audio Interface ........................................................................ 13 Figure 20. OVFL Output Timing, I2S Format ............................................................ 13 Figure 21. OVFL Output Timing, Left-Justified Format ............................................. 13 Figure 22. Typical Connection Diagram ................................................................... 15 Figure 23. CS5361 Master Mode Clocking ............................................................... 17 Figure 24. CS5361 Recommended Analog Input Buffer .......................................... 18
LIST OF TABLES
Table 1. Table 2. Table 3. Table 4. CS5361 Mode Control .............................................................................. 16 CS5361 Slave Mode Clock Ratios ........................................................... 16 CS5361 Common Master Clock Frequencies .......................................... 17 Revision History ....................................................................................... 23
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1.0 CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the specified operating conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TA = 25C.
SPECIFIED OPERATING CONDITIONS
GND = 0 V, all voltages with respect to GND. Parameter DC Power Supplies: Positive Analog Positive Digital Positive Logic Commercial (-KSZ/-KZZ) Automotive (-DZZ) Symbol VA VD VL TAC TAA Min 4.75 3.1 2.37 -10 -40 Typ 5.0 3.3 3.3 Max 5.25 5.25 5.25 70 85 Unit V V V C C
Ambient Operating Temperature
ABSOLUTE MAXIMUM RATINGS
GND = 0 V, All voltages with respect to GND. (Note 1) Parameter DC Power Supplies: Analog Logic Digital (Note 2) (Note 3) (Note 3) Symbol VA VL VD Iin VIN VIND TA Tstg Min -0.3 -0.3 -0.3 -10 - 0.7 -0.7 -50 -65 Max +6.0 +6.0 +6.0 +10 VA + 0.7 VL + 0.7 +95 +150 Units V V V mA V V C C
Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature
Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current.
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ANALOG CHARACTERISTICS (CS5361-KSZ/KZZ)
Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Parameter Single Speed Mode Fs = 48 kHz Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB Double Speed Mode Fs = 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Quad Speed Mode Fs = 192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Dynamic Performance for All Modes Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Error HPF enabled HPF disabled Analog Input Characteristics Full-scale Input Voltage Input Impedance (Differential) (Note 5) Common Mode Rejection Ratio Symbol Min 108 105 THD+N 108 105 THD+N 108 105 THD+N -2 -100 1.10*VA 7.5 -105 -91 -51 -102 110 0.1 1.13*VA 82 -99 2 100 0 100 1.15*VA dB dB dB dB dB dB % ppm/C LSB LSB Vpp k dB -105 -91 -51 -102 114 111 108 -99 dB dB dB dB dB dB dB -105 -91 -51 114 111 108 -99 dB dB dB dB dB dB Typ 114 111 Max Unit dB dB
CMRR
Notes: 4. Referred to the typical full-scale input voltage. 5. Measured between AIN+ and AIN-
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ANALOG CHARACTERISTICS (CS5361-DZZ)
Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Parameter Single Speed Mode Dynamic Range Symbol Min 106 103 THD+N 106 103 THD+N 106 103 THD+N -5 -100 1.07*VA 7.5 -105 -91 -51 -102 110 0.0001 0.1 1.13*VA 82 -95 5 100 0 100 1.18*VA dB dB dB dB dB Degree dB % ppm/C LSB LSB Vpp k dB -105 -91 -51 -102 114 111 108 -95 dB dB dB dB dB dB dB -105 -91 -51 114 111 108 -95 dB dB dB dB dB dB Typ 114 111 Max Unit dB dB
Fs = 48 kHz A-weighted unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB Double Speed Mode Fs = 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Quad Speed Mode Fs = 192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Dynamic Performance for All Modes Interchannel Isolation Interchannel Phase Deviation DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Error HPF enabled HPF disabled Analog Input Characteristics Full-scale Input Voltage Input Impedance (Differential) (Note 5) Common Mode Rejection Ratio
CMRR
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DIGITAL FILTER CHARACTERISTICS
Parameter Single Speed Mode (2 kHz to 51 kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Interchannel Phase Deviation Double Speed Mode (50 kHz to 102 kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Interchannel Phase Deviation Quad Speed Mode (100 kHz to 204 kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Interchannel Phase Deviation High-pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time Notes: 6. The filter frequency response scales precisely with Fs. 7. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. -3.0 dB -0.13 dB @ 20 Hz (Note 7) (Note 7) 1 20 10 105/Fs 0 Hz Hz Deg dB s tgd (Note 6) (-0.1 dB) (Note 6) 0 -0.1 0.78 -92 5/Fs 0.0001 0.24 0.035 Fs dB Fs dB s Deg tgd (Note 6) (-0.1 dB) (Note 6) 0 -0.1 0.68 -92 9/Fs 0.0001 0.45 0.035 Fs dB Fs dB s Deg tgd (Note 6) (-0.1 dB) (Note 6) 0 -0.1 0.58 -95 12/Fs 0.0001 0.47 0.035 Fs dB Fs dB s Deg Symbol Min Typ Max Unit
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0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
Amplitude (dB)
Amplitude (dB)
-60 -70 -80 -90 -100 -110 -120 -130 -140 0.40
-60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
Figure 1. Single Speed Mode Stopband Rejection
Figure 2. Single Speed Mode Transition Band
0
0.10
-1
0.08
-2
0.05
-3
0.03 Amplitude (dB)
Amplitude (dB)
-4
-5
0.00
-6
-0.03
-7
-0.05
-8
-0.08
-9
-0.10 0.00
-10 0.45
0.46
0.47
0.48
0.49
0.50
0.51
0.52
0.53
0.54
0.55
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 3. Single Speed Mode Transition Band (Detail)
Figure 4. Single Speed Mode Passband Ripple
0 -10 -20 -30 -40 -50 Amplitude (dB) Amplitude (dB) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -60 -70 -80 -90 -100 -110 -120 -130 -140 Frequency (normalized to Fs)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40
0.43
0.45
0.48
0.50
0.53
0.55
0.58
0.60
0.63
0.65
0.68
0.70
Frequency (normalized to Fs)
Figure 5. Double Speed Mode Stopband Rejection
Figure 6. Double Speed Mode Transition Band
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0
0.10
-1
0.08
-2 0.05 -3 0.03 Amplitude (dB) 0.43 0.45 0.48 Frequency (normalized to Fs) 0.50 0.53 0.55
Amplitude (dB)
-4
-5
0.00
-6
-0.03
-7 -0.05 -8 -0.08
-9
-10 0.40
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 7. Double Speed Mode Transition Band (Detail)
Figure 8. Double Speed Mode Passband Ripple
Amplitude (dB)
F r e q u e n c y ( n o r m a liz e d t o F s )
Amplitude (dB)
F re q u e n c y ( n o rm a liz e d t o F s )
Figure 9. Quad Speed Mode Stopband Rejection
Figure 10. Quad Speed Mode Transition Band
Amplitude (dB)
Amplitude (dB)
F re q u e n c y ( n o rm a liz e d t o F s )
F re q u e n c y ( n o rm a liz e d to F s )
Figure 11. Quad Speed Mode Transition Band (Detail)
Figure 12. Quad Speed Mode Passband Ripple
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DC ELECTRICAL CHARACTERISTICS
GND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Master Mode. Parameter Power Supply Current (Normal Operation) Power Supply Current (Power-Down Mode) (Note 8) Power Consumption (Normal Operation) VA = 5 V VL,VD = 5 V VL,VD = 3.3 V VA = 5 V VL,VD = 5 V VA, VD, VL = 5 V VA = 5 V, VL, VD = 3.3 V (Power-Down Mode) (Note 9) Symbol IA ID ID IA ID PSRR Min Typ 17.5 22 14.5 100 100 198 135 1 65 2.5 25 0.01 5 15 0.01 Max 21.5 27.5 17 243 161 Unit mA mA mA A A mW mW mW dB V
Power Supply Rejection Ratio (1 kHz) VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink
k
mA V
k
mA
Notes: 8. Power Down Mode is defined as RST = Low with all clocks and data lines held static. 9. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram.
DIGITAL CHARACTERISTICS
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io = 100 A Low-Level Output Voltage at Io = 100 A OVFL Current Sink Input Leakage Current (all pins except SCLK and LRCK) Input Leakage Current (SCLK and LRCK) (% of VL) (% of VL) (% of VL) (% of VL) Symbol VIH VIL VOH VOL Iovfl Iin Iin Min 70% 70% -10 -25 Typ Max 30% 15% 4.0 10 25 Units V V V V mA A A
THERMAL CHARACTERISTICS
Parameter Allowable Junction Temperature Junction to Ambient Thermal Impedance (Multi-layer PCB) TSSOP (Multi-layer PCB) SOIC (Single-layer PCB) TSSOP (Single-layer PCB) SOIC Symbol Min Typ 70 60 105 80 Max 135 Unit C C/W C/W C/W C/W
JA-TM JA-SM JA-TS JA-SS
-
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SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF Parameter Output Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Symbol Fs Fs Fs tsetup thold Min 2 50 100 16/fsclk 1/fsclk tclkw 38 40 tmslr tsdo -20 0 Typ 740 680 50 50 Max 51 102 204 1953 60 20 32 Unit kHz kHz kHz s s ms ms ns % ns ns %
OVFL to LRCK edge setup time OVFL to LRCK edge hold time OVFL time-out on overrange condition Fs = 44.1, 88.2, 176.4 kHz Fs = 48, 96, 192 kHz MCLK Specifications MCLK Period MCLK Pulse Duty Cycle Master Mode SCLK falling to LRCK SCLK falling to SDOUT valid SCLK Duty Cycle Slave Mode Single Speed Output Sample Rate LRCK Duty Cycle SCLK Period SCLK Duty Cycle SCLK falling to SDOUT valid SCLK falling to LRCK edge Double Speed Output Sample Rate LRCK Duty Cycle SCLK Period SCLK Duty Cycle SCLK falling to SDOUT valid SCLK falling to LRCK edge Quad Speed Output Sample Rate LRCK Duty Cycle SCLK Period SCLK Duty Cycle SCLK falling to SDOUT valid SCLK falling to LRCK edge
Fs tsclkw tdss tslrd Fs tsclkw tdss tslrd Fs tsclkw tdss tslrd
2 40 153 45 -20 50 40 153 45 -20 100 40 77 45 -8
50 50 50 50 50 50 -
51 60 55 32 20 102 60 55 32 20 204 60 55 32 3
kHz % ns % ns ns kHz % ns % ns ns kHz % ns % ns ns
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SCLK output
CLK input
tmslr LRCK output tsdo SDOUT MSB MSB-1
SDOUT LRCK input
t slrd
t sclkw
t dss MSB MSB-1 MSB-2
Figure 13. Master Mode, Left Justified SAI
Figure 14. Slave Mode, Left Justified SAI
SCLK input t slrd LRCK input t dss SDOUT MSB MSB-1 tsclkw
SCLK input t slrd LRCK input t dss SDOUT MSB MSB-1 tsclkw
Figure 15. Master Mode, I2S SAI
Figure 16. Slave Mode, I2S SAI
LRCK t setup OVFL t hold
Figure 17. OVFL Output Timing
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LRCK
Left Channel
Right Channel
SCLK
SDATA
23 22
9876543210
23 22
9876543210
23 22
Figure 18. Left Justified Serial Audio Interface
LRCK
Left Channel
Right Channel
SCLK
SDATA
23 22
9876543210
23 22
9876543210
23 22
Figure 19. I2S Serial Audio Interface
LRCK
SCLK
O VFL
O VFL_R
O VFL_L
O VFL_R
Figure 20. OVFL Output Timing, I2S Format
LR CK
SCLK
OVFL
O VFL_R
O VFL_L
O VFL_R
Figure 21. OVFL Output Timing, Left-Justified Format
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2.0 PIN DESCRIPTIONS
RST M/S LRCK SCLK MCLK VD GND VL SDOUT MDIV HPF I2S/LJ 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FILT+ REFGND VQ AINR+ AINRVA GND AINLAINL+ OVFL M1 M0
Pin Name
RST M/S LRCK SCLK MCLK VD GND VL SDOUT MDIV HPF I S/LJ M0 M1 OVFL AINL+ AINLVA AINRAINR+ VQ REF_GND FILT+
2
# 1 2 3 4 5 6 8 9 10 11 12
Pin Description
Reset (Input) - The device enters a low power mode when low. Master/Slave Mode (Input) - Selects operation as either clock master or slave. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Digital Power (Input) - Positive power supply for the digital section.
7,18 Ground (Input) - Ground reference. Must be connected to analog ground.
Logic Power (Input) - Positive power for the digital input/output. Serial Audio Data Output (Output) - Output for two's complement serial audio data. MCLK Divider (Input) - Enables a master clock divide by two function. High-pass Filter Enable (Input) - Enables the Digital High-Pass Filter. Serial Audio Interface Format Select (Input) -Selects either the left-justified or I2S format for the SAI.
13, Mode Selection (Input) - Determines the operational mode of the device. 14 15
Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.
16, Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma 17 modulators via the AINL+/- pins. 19
Analog Power (Input) - Positive power supply for the analog section.
20, Differential Right Channel Analog Input (Input) -Signals are presented differentially to the delta-sigma 21 modulators via the AINR+/- pins. 22 23 24
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. Reference Ground (Input) - Ground reference for the internal sampling circuits. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
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3.0 TYPICAL CONNECTION DIAGRAM
+5 V to 3.3 V + 1 F 0.01F
*
0.01 F 0.01F
+
1 F
+5Vto 2.5 V
+5V
+
1 F
0.01 F
5.1 VD
VA FILT+ **47 F + 0.01 F REFGND + 1 F 0.01 F VQ
VL VL 10 k OVFL RST 2 I S/LJ M/S HPF M0 M1 MDIV
Analog Input Buffer (Figure 24)
AINL+
CS5361 A/D CONVERTER
Power Down and Mode Settings
AINLSDOUT Audio Data Processor
Analog Input Buffer (Figure 24)
AINR+
LRCK SCLK MCLK Timing Logic and Clock
AINR* Resistor may only be used if VD is derived from VA. If used, do not drive any other logic from VD.
GND
GND
Figure 22. Typical Connection Diagram
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4.0 APPLICATIONS 4.1 Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2 kHz to 204 kHz. The CS5361 must be set to the proper speed mode via the mode pins, M1 and M0. Refer to Table 1. M1 (Pin 14) 0 0 1 1 M0 (Pin 13) 0 1 0 1 MODE Single Speed Mode Double Speed Mode Quad Speed Mode Reserved Table 1. CS5361 Mode Control Output Sample Rate (Fs) 2 kHz - 51 kHz 50 kHz - 102 kHz 100 kHz - 204 kHz
4.2
System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchronously generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks. The device also includes a master clock divider in Master Mode where the master clock will be internally divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV pin needs to be disabled, set to logic 0.
4.2.1
Slave Mode
LRCK and SCLK operate as inputs in Slave mode. The left/right clock must be synchronously derived from the master clock and be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance. Refer to Table 2 for required clock ratios. Single Speed Mode Fs = 2 kHz to 51 kHz MCLK/LRCK Ratio SCLK/LRCK Ratio 256x, 512x 32x, 64x, 128x Double Speed Mode Fs = 50 kHz to 102 kHz 128x, 256x 32x, 64x Quad Speed Mode Fs = 100 kHz to 204 kHz 128x 32x, 64x
Table 2. CS5361 Slave Mode Clock Ratios
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4.2.2 Master Mode
In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 23. Refer to Table 3 for common master clock frequencies.
/ 256 / 128 / 64 /1 MCLK /2 1 /4 MDIV /2 /1 0
Single Speed Double Speed Quad Speed
00 01 10
LRCK Output (Equal to Fs)
M1
M0
Single Speed Double Speed Quad Speed
00 01 10
SCLK Output
Figure 23. CS5361 Master Mode Clocking
SAMPLE RATE (kHz) 32 44.1 48 64 88.2 96 176.4 192
MDIV = 0 MCLK (MHz) 8.192 11.2896 12.288 8.192 11.2896 12.288 11.2896 12.288
MDIV = 1 MCLK (MHz) 16.384 22.5792 24.576 16.384 22.5792 24.576 22.5792 24.576
Table 3. CS5361 Common Master Clock Frequencies
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4.3 Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a delay between the release of reset and the generation of valid output, due to the finite output impedance of FILT+ and the presence of the external capacitance.
4.4
Analog Connections
The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n x 6.144 MHz) the digital passband frequency, where n=0,1,2,...Refer to Figure 24 which shows the suggested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity.
634
470 pF COG 10 uF AIN+ 100 k 10 k COG VQ 10 k 10 uF AIN100 k + 470 pF COG 634 91 ADC AIN2700 pF + 91 ADC AIN+
Figure 24. CS5361 Recommended Analog Input Buffer
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4.5 High-pass Filter and DC Offset Calibration
The operational amplifiers in the input circuitry driving the CS5361 may generate a small DC offset into the A/D converter. The CS5361 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPF pin is taken high during normal operation, the current value of the DC offset register is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1) Running the CS5361 with the high-pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2) Disabling the high-pass filter and freezing the stored DC offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS5361.
4.6
Overflow Detection
The CS5361 includes overflow detection on both the left and right channels. This time multiplexed information is presented as open drain, active low on pin 15, OVFL. The OVFL_L and OVFL_R data will go to a logical low as soon as an overrange condition in either channel is detected. The data will remain low as specified in the Switching Characteristics - Serial Audio Port section. This ensures sufficient time to detect an overrange condition regardless of the speed mode. After the timeout, the OVFL_L and OVFL_R data will return to a logical high if there has not been any other overrange condition detected. Please note that an overrange condition on either channel will restart the timeout period for both channels.
4.6.1
OVFL Output Timing
In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I2S format, the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to Figures 23 and 24. In both cases the OVFL data can be easily demultiplexed by using the LRCK to latch the data. In left-justified format, the rising edge of LRCK would latch the right channel overflow status, and the falling edge of LRCK would latch the left channel overflow status. In I2S format, the falling edge of LRCK would latch the right channel overflow status and the rising edge of LRCK would latch the left channel overflow status.
4.7
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS5361 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 22 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.01 F, must be positioned to minimize the electrical path from FILT+ and REFGND. The CDB5361 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
4.8
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5361's in the system. If only one master clock source is needed, one solution is to place one CS5361 in Master mode, and slave all of the other CS5361's to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS5361 reset with the inactive edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.
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CS5361
5.0 PARAMETER DEFINITIONS
Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
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6.0 PACKAGE DIMENSIONS
24L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1 b c D SEATING PLANE e A1 L A
INCHES DIM A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.598 0.291 0.040 0.394 0.016 0 MAX 0.104 0.012 0.020 0.013 0.614 0.299 0.060 0.419 0.050 8
MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 15.20 15.60 7.40 7.60 1.02 1.52 10.00 10.65 0.40 1.27 0 8
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CS5361
24L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e b2 SIDE VIEW
123
END VIEW
SEATING PLANE
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.03346 0.00748 0.303 0.248 0.169 -0.020 0 NOM -0.004 0.0354 0.0096 0.307 0.2519 0.1732 0.026 BSC 0.024 4 MAX 0.043 0.006 0.037 0.012 0.311 0.256 0.177 -0.028 8 MIN -0.05 0.85 0.19 7.70 6.30 4.30 -0.50 0
MILLIMETERS NOM --0.90 0.245 7.80 6.40 4.40 0.65 BSC 0.60 4 MAX 1.10 0.15 0.95 0.30 7.90 6.50 4.50 -0.70 8
NOT E
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1."D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2.Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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7.0 REVISION HISTORY
Release PP3 PP4 F1 Date Mar 2003 Sept 2004 Jan 2005 Changes Preliminary datasheet. Include lead-free device ordering info. Improve Gain Error specification under Analog Characteristics. Specify Full-scale Input Voltage in terms of VA under Analog Characteristics. Update Differential Input Impedance under Analog Characteristics. Increase maximum THD+N rating for automotive grade devices. Increase maximum Power-Supply Current, IA, under DC Electrical Characteristics. Reduce maximum Power Consumption under DC Electrical Characteristics. Update FILT+ Output Impedance specification under DC Electrical Characteristics. Extend maximum Fs in Single-Speed Mode to 51 kHz. Extend maximum Fs in Double-Speed Mode to 102 kHz. Extend maximum Fs in Quad-Speed Mode to 204 kHz. Decrease maximum SCLK falling to LRCK edge specification in Quad-Speed Mode. Replace minimum MCLK high/low timing specifications with duty cycle specification. Replace minimum SCLK high/low timing specifications with duty cycle specification. Correct Recommended Analog Input Circuit.
Table 4. Revision History
F2
Feb 2005
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
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